1. Field of the Invention
This invention relates to the control of multi-block semiconductor SRAM, and more particularly to the generation of memory control pulses.
2. Description of the Related Art
Recent designs of Megabit semiconductor SRAM (static random access memory) are generally based on a multi-block architecture as shown in FIG. 1. The multi-block architecture design results in power saving and memory speed improvement. The central control generates global signals which are distributed to each memory block where they are used directly or are decoded to produce required local control signals. The larger the size of the SRAM, the longer the distribution paths for the global control signals. The global control pulse signals travel to each memory block and have different wire loading and fan-out loading causing a variation in delay at each memory block. Memory design requires a specific relationship between the leading and trailing edges of control pulse signals. The differences in loading and fan-out result in variation in skew of these control pulses. In high speed memories, these variations in loading and fan-out are significant and limit the speed of memory operation by requiring sufficient timing margins to accommodate worst case skews.
FIG. 2 and FIG. 3 illustrate the effect of skew on the timing relationship between memory control pulses for Read and Write operations respectively. The correct timing relationship between the memory control pulses exists at the output of the Central Control (FIG. 2A). These are globally distributed to each memory control block. These signal pulses have varied delays as they propagate through the system which affects the timing relationships between the pulses. In the extreme case, the resultant skew may be large enough to cause memory malfunction. This is illustrated for the Read operation in FIG. 2. Two cases are shown. In case 1 (FIG. 2C) the Word-Line pulse has a greater delay than SA enable. The limit at which the timing relationship is still maintained is shown occurring at Block M (FIG. 2B). In subsequent memory blocks the skew exceeds the required timing criteria resulting in operational failure, as illustrated for Block N. In case 2 (FIG. 2D and FIG. 2E) an analogous situation occurs affecting the trailing edge timing relationships. FIG. 3 illustrates similar situations for the memory Write operation.
Four known U.S. patents deal with multi-block systems involving either global interconnection or local generation of control signals.
U.S. Pat. No. 5,837,557 (Fulford, Jr. et al) describes a semiconductor structure consisting of multiple circuit blocks which are globally interconnected by means of a blanket metal layer. The structure described in the patent allows a reduction of overall circuit size, enhanced circuit quality and improvements in fabrication time and costs.
U.S. Pat. No. 5,581,126 (Moench) deals with the layout of interconnect lines within integrated circuits. It is the object of the invention to eliminate data pattern sensitivity and unwanted differential signals in SRAM arrays due to lateral capacitive coupling from adjacent lines. This is accomplished by using a crossover structure to reduce the effect of parasitic capacitance.
U.S. Pat. No. 5,243,703 (Farmwald et al) describes a method for generating a synchronized clock pulse at each device block in a computer memory system consisting of multiple blocks. This is done with a single globally generated clock pulse that is transmitted to each of the blocks via a looped path. Each block receives one input from the forward half of the loop and another input from the return half of the loop. This allows each block to generate a clock pulse with synchronized timing. The patent does not address the problem of control pulse skew as described by the present invention.
U.S. Pat. No. 4,926,384 (Roy) deals with SRAM write cycle recovery timing. The patent describes an SRAM composed of multiple separate memory blocks where each block has its own local bit line equalization circuitry. This removes the process of equalizing the bit lines after a write cycle from the critical timing path for accessing the memory. The patent also provides means for automatically equalizing the common data out lines at the end of each memory access cycle which removes the process of equalizing the common data out lines from the critical timing path for accessing the memory.